AgateLogic 2009年校园招聘 的, 公司, structured, Software, 软件工具

klfeixiang

公司简介
雅格罗技（北京）科技有限公司是Agate Logic, Inc. 在北京的研发中心，也是国内第一家专业从事FPGA与structured ASIC研发的公司。公司拥有多项自主知识产权和核心技术，致力于对可配置可编程系统芯片（Configurable and Programmable System on Chip）以及相关面向客户的电子设计自动化软件工具（EDA Software Tool）进行全方位研发。

作为全球APGA（Adaptable Programmable Gate Array）技术的首创者和领导者，Agate Logic为客户提供了基于我公司自主研发的FPGA技术的SoC系统服务，其中包括FPGA芯片、EDA软件及配套的应用。采用本土化的芯片制造商，目标定位于多种应用类市场领域，为用户提供通用芯片设计平台和一套完整高效的EDA设计软件，使设计者们能够更加便捷、灵活、快速地实现产品设计，降低市场进入成本，让客户随“芯”所欲。

公司研发中心现位于北京市中关村科技园区的清华科技园。吸纳优秀的软件和硬件技术人才是确保我公司保持健康成长的关键。我们热情邀请各位有激情、有梦想的有志之士加入我们的研发团队，共同进步，共创辉煌！

地址：北京海淀区清华科技园创业大厦
Email: hr@agatelogic.com.cn

招聘职位
Jobs Title: IC Design Engineer
Job Responsibility:
  As an IC Design Engineer, you will be a key member of the Architecture group. You will assist on the development of architecture and participate in design/verification of RTL, circuit and layout of the core of our chip.
Requirements:
- MSEE/CS or above
- Have solid knowledge and understanding of IC basics, including the circuit structure and behavioral of NMOS/CMOS transistor and gate
- Have high speed logic design, verification and STA experience with Verilog, either on FPGA or for ASIC
- Ability to work in a team and to closely interact with other groups
- Experience of scripting with Tcl / Perl / Python
Preferences:
- Know well ASIC design flow and design tools from RTL to GDS
- Know well FPGA architecture
- Good at English writing and speaking

Job Title: Software Design Engineer
Job Responsibility:
  As an SW Design Engineer, you will be a key member of the Architecture group. You will participate in the development of SW tool for architecture evaluation and development, including 2D and 3D graphic modeling and automatic routing and drawing
Requirements:
- MSEE/CS or above
- Excellent programming skills in object-oriented design, C++
- Have experience of 2D or 3D graphic relative software design
- Ability to work in a team and to closely interact with other groups
Preferences:
- Knowledge of network switch architecture and network routing algorithm
- Familiar with Windows programming, Qt, Linux and GCC
- Skillful in shell scripts, Python, and/or TCL

Job Title: EDA Software (Algorithm) Engineer    
Job Responsibilities:
With help from senior staff, specify, design, implement and test software components as part of a modern state-of-the-art EDA design tool chain supporting our configurable system-on-chip solutions.
Requirements:
- M.S., or B.S. with 2 years of experience in related areas;
- At least 2 plus years of experience in software development with talents in algorithm design;
- Excellent strong programming skills in object-oriented design, C++;
- Good team player with communication skill.
Preferences:
- Experience with algorithms used in RTL/logic synthesis, technology mapping, placement, routing, timing models and analysis, and/or FPGA architectures;
- Related courses or work in design automation for digital systems;
- Familiar with shell scripts, Python, Perl and/or Tcl.

Job Title：FPGA Application Engineer
Job Responsibilities:
Responsible for providing support for customers logic and/or system design. Support in-depth technical inquiries, providing design evaluations and recommendations, and creating technical collaterals including documentation, design examples and demos. Work with the development teams to provide feedback to improve Agate’s design tools and methodology. Seniority depends on levels of experience.
Requirements:
- BSEE or equivalent with 2+ years, or a MSEE with 1+ years of relevant project experience.
- At least 1 to 2 years of FPGA design experience.
- Familiar with the software and hardware design using MCU products.
- Familiar with Verilog HDL and/or VHDL.
- Familiar with assembly language and/or C language.
- Capable of working in a team and skillful in communication
Preferences:
- System level experience with FPGA architectures, microprocessors, memory controllers, DSP, networking, storage, and communications.
- Skillful in high-speed board level system design.
- Familiarity with Synopsys Design Compiler and Synplicity.
- Skillful in C++, shell scripts, Python, and/or Perl.

Job Title: Hardware IP Design Engineer
Job Responsibilities:
With help from senior staff, specify, design, implement, verify and document hardware re-usable HDL modules optimized for structured ASIC or FPGA device architectures.
Requirements:
- M.S. or B.S. with at least 2 years of relevant experience.
- Solid design experience with Verilog and/or VHDL, logic synthesis, simulation and verification tools.
- Have a track record of successful completion of complex design projects for at least 1 year
- Good programming skills in C.
Preferences:
- System level experience with FPGA architectures, microprocessors, memory controllers, DSP, networking, storage, and communications.
- Familiarity with Synopsys Design Compiler, ModelSim, PrimeTime.
- Skillful in C, C++, shell scripts, Python, and/or Perl.

Job Title：System Test Engineer
Job Responsibilities:
Perform system-level testing, including chip, firmware, application and in-house EDA software tests
Requirements:
- MS, or BS with at least 2 years of experience in FPGA/MCU applications
- Familiar with Hardware description language (Verilog/VHDL)
- Programming skills in C, C++.
- Familiar with popular MCU, such as 8051, MIPS and/or ARM.
Preferences:
- Familiar with FPGA.


* 投递简历请发送至hr@agatelogic.com.cn
* 邮件主题请注明来自水木
* 简历符合条件者，一周内通知面试